Design Principal Manufacturing Process Design Package

Focusing on resources for the wafer design process according to our clients' needs, Powerchip has developed a complete design principal manufacturing process design package; after signing a confidential agreement (NDA), clients can download relevant packages through our online ePowerchip network interface in order to accelerate the chip/wafer design process.

Powerchip's manufacturing process design packages include the following items:

  • Design Rule (Layout rule/ESD/Latch up/Antenna/CMP/……)
  • Device Parameter(EDR)
  • DRC/LVS command file (calibre)
  • SPICE model
  • Standard Cell Library / IO Cell Library
  • RC technology file (Calibre XRC/Star-RC)
  • Layout technology file (Laker/Virtuoso)
  • Layout Example (Device/Fuse/SRAM/ESD/……)